Integrated circuits are commonly made incorporating as the substrate thereof a thin sheet material referred to as ceramic greensheet or just greensheet. Conductive patterns may be screened onto one or both surfaces of such ceramic greensheets and conductive passageways therethrough, known as vias, are formed by punching holes in the greensheet and filling the holes with conductive paste which hardens into an electrical conductor. This serves to connect conductive elements on the two sides of the greensheet or to conductive elements on adjacent greensheets or to soldered connections.
Because of the extremely small size of such integrated circuits, surface imperfections in the conductive vias may cause problems in the subsequent connection or assembly of the substrate. Depressions in a surface via, for example, may entrap flux during chip joining such that outgassing occurs and forms voids in a solder joint at the depression-including surface of the via. Such voids can be detrimental to the performance, reliability, or both performance and reliability of the joint. Similarly, a via protuberance, above the surrounding surface of the ceramic greensheet, may cause a corresponding surface imperfection in a conductive element screened over, and making electrical connection with, this via surface.
Conventional attempts to minimize protuberances and depressions in the exposed surfaces of the conductive vias formed in a surrounding greensheet integrated circuit substrate have not been entirely successful. A need exists, therefore, for an improved method for forming conductive vias in a surrounding greensheet integrated circuit substrate wherein protuberances and depressions in the exposed surfaces of the vias are minimized. Accordingly, forming conductive vias in a ceramic greensheet, while minimizing depressions and protuberances in the exposed surface of the conductive via, is a common object.